ARM Cortex-M0+ Architecture Basics
Based upon Harvard Architecture, the LPC812 uses an ARM Cortex-M0+ processor. This means it has separate instruction (flash) and data (SRAM) memory. The basic architecture includes the core components and peripherals.
The core consists of:
- Pin interrupts
- Multi-rate Timer
- Watchdog Timer
All output is routed through the Switch Matrix to the individual pins. The switch matrix allows the flexibility of swapping the digital peripheral functions amongst the pins. Obviously, the basic functions like GPIO, power, ground and some others cannot be swapped.
LPC81x Block Diagram
Fortunately for us, we don’t need to focus too much on the internal design. The main factor to remember is the peripherals are memory mapped. This means our interaction with them (configuration, control, input, and output) is accomplished through an address. Accessing a peripheral is just like writing or reading a value in memory.
It is good practice to access peripherals using a read-modify-write strategy. This strategy is seen throughout ARM and LPC examples.
GPIO_DIR |= (1<<9); //proper method preserves unaffected bits of register //assembler translation: 0xd6: 0x4813 LDR.N R0, [PC, #0x4c] ; [0x124] DIR0 0xd8: 0x6800 LDR R0, [R0] 0xda: 0x2180 MOVS R1, #128 ; 0x80 0xdc: 0x0089 LSLS R1, R1, #2 0xde: 0x4301 ORRS R1, R1, R0 0xe0: 0x4810 LDR.N R0, [PC, #0x40] ; [0x124] DIR0 0xe2: 0x6001 STR R1, [R0] … 0x124: 0xa0002000 DC32 DIR0 // // // GPIO_DIR = (1<<9); //improper method clobbers all bit of the register //assembler translation: 0xc2: 0x2080 MOVS R0, #128 ; 0x80 0xc4: 0x0080 LSLS R0, R0, #2 0xc6: 0x4911 LDR.N R1, [PC, #0x44] ; [0x10c] DIR0 0xc8: 0x6008 STR R0, [R1] … 0x10c: 0xa0002000 DC32 DIR0
Flash, SRAM and ROM memory
The LPC81xM contain up to 16kB of flash program memory, a total of up to 4kB static RAM data memory, and 8kB of on-chip ROM. The ROM contains the boot loader and In-System Programming (ISP) and In-Application Programming (IAP) support for flash programming, profiles for configuring power consumption and PLL settings, USART driver API routines, and I2C-bus driver routines.
The Very Basic Memory Map
0x00000000 - 0x00004000: Flash program memory
0x10000000 - 0x10001000: SRAM memory
0x1FFF0000 - 0x1FFF2000: Boot ROM (8kB)
0x40000000 - 0x40070000: All APB peripherals
0x50004000 - 0x50008000: SCTimer/PWM
0xA0000000 - 0xA0008000: GPIO
My next post about ARM Cortex-M0.